10 search results - page 1 / 2 » Redundant wire insertion for yield improvement |
GLVLSI
2009
IEEE
14 years 31 min ago
2009
IEEE
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
ASPDAC
2009
ACM
13 years 8 months ago
2009
ACM
—Redundant via insertion is a widely recommended technique to enhance the via yield and reliability. In this paper, the post-routing redundant via insertion problem is transforme...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...