6 search results - page 1 / 2 » Register binding for clock period minimization |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...