Timing driven power gating in high-level synthesis

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Timing driven power gating in high-level synthesis
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work to draw up the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show: compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.
Shih-Hsu Huang, Chun-Hua Cheng
Added 28 May 2010
Updated 28 May 2010
Type Conference
Year 2009
Authors Shih-Hsu Huang, Chun-Hua Cheng
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