33 search results - page 5 / 7 » Register placement for high-performance circuits |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
ICCD
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...