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DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 3 days ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
TCAD
1998
127views more  TCAD 1998»
13 years 5 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
TVLSI
2008
139views more  TVLSI 2008»
13 years 5 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 11 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
EWSN
2009
Springer
14 years 17 days ago
SCOPES: Smart Cameras Object Position Estimation System
In this paper we present SCOPES, a distributed Smart Camera Object Position Estimation sensor network System that provides maps of distribution of people in indoors environments. ...
Ankur Kamthe, Lun Jiang, Matthew Dudys, Alberto Ce...