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» Regular layout generation of logically optimized datapaths
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ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
13 years 9 months ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk
ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
14 years 1 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch
DAC
1998
ACM
14 years 5 months ago
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...
Alexander Grießing, Paolo Ienne
DAC
2000
ACM
13 years 9 months ago
Macro-driven circuit design methodology for high-performance datapaths
Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom st...
Mahadevamurty Nemani, Vivek Tiwari
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 2 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...