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» Reliability- and process variation-aware placement for FPGAs
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FPL
2006
Springer
137views Hardware» more  FPL 2006»
13 years 8 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
DAC
2006
ACM
14 years 5 months ago
Process variation aware OPC with variational lithography modeling
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional ...
Peng Yu, Sean X. Shi, David Z. Pan
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 9 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
13 years 11 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
JCP
2008
105views more  JCP 2008»
13 years 4 months ago
Thermal Driven Placement for Island-style MTCMOS FPGAs
Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots...
Javid Jaffari, Mohab Anis