4 search results - page 1 / 1 » Repeater and current-sensing hybrid circuits for on-chip int... |
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
