19 search results - page 4 / 4 » Repeater insertion and wire sizing optimization for throughp... |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
ISPD
2005
ACM
13 years 10 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
INTEGRATION
2006
13 years 4 months ago
2006
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...