13 search results - page 2 / 3 » Robust analytical gate delay modeling for low voltage circui... |
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...