14 search results - page 1 / 3 » Robust testability of primitive faults using test points |
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
ITC
1994
IEEE
13 years 9 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
IOLTS
2006
IEEE
13 years 11 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
ARVLSI
1999
IEEE
13 years 9 months ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...