17 search results - page 3 / 4 » S-Tree: a technique for buffered routing tree synthesis |
DAC
2006
ACM
13 years 11 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, pow...
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ISQED
2007
IEEE
14 years 1 days ago
2007
IEEE
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
DSD
2007
IEEE
14 years 3 days ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...