63 search results - page 12 / 13 » SADL: Simulation Architecture Description Language |
FDL
2005
IEEE
13 years 10 months ago
2005
IEEE
Embedded system designs and simulations become tedious and time consuming due to the complexity of modern applications. Thus, languages allowing high level description, such as Sy...
DATE
2009
IEEE
13 years 12 months ago
2009
IEEE
– In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to ...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) so...