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» SP4: scalable programmable packet processing platform
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ANCS
2007
ACM
13 years 9 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
FPL
2005
Springer
111views Hardware» more  FPL 2005»
13 years 11 months ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....
FPL
2006
Springer
105views Hardware» more  FPL 2006»
13 years 9 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
ICDM
2010
IEEE
189views Data Mining» more  ICDM 2010»
13 years 3 months ago
S4: Distributed Stream Computing Platform
Abstract--S4 is a general-purpose, distributed, scalable, partially fault-tolerant, pluggable platform that allows programmers to easily develop applications for processing continu...
Leonardo Neumeyer, Bruce Robbins, Anish Nair, Anan...
ANCS
2009
ACM
13 years 3 months ago
SANS: a scalable architecture for network intrusion prevention with stateful frontend
Inline stateful and deep inspection for intrusion prevention is becoming more challenging due to the increase in both the volume of network traffic and the complexity of the analy...
Fei He, Yaxuan Qi, Yibo Xue, Jun Li