This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...