11 search results - page 1 / 3 » Scalable interprocedural register allocation for high level ... |
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
ASAP
2007
IEEE
13 years 6 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
DAC
1989
ACM
13 years 8 months ago
1989
ACM
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
TVLSI
2008
13 years 4 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...