3 search results - page 1 / 1 » Scalable performance scheduling for hardware-software cosynt... |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...