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» Scaling, Power and the Future of CMOS
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DAC
2006
ACM
14 years 6 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 9 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
DATE
2008
IEEE
133views Hardware» more  DATE 2008»
13 years 11 months ago
Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges
Future system design methodologies must accept the fact that the underlying hardware will be imperfect, and enable design of robust systems that are resilient to hardware imperfec...
Subhasish Mitra
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
13 years 10 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...
ISQED
2007
IEEE
179views Hardware» more  ISQED 2007»
13 years 11 months ago
Cross Layer Error Exploitation for Aggressive Voltage Scaling
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used t...
Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Ku...