86 search results - page 17 / 18 » Scaling and Packing on a Chip Multiprocessor |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
MOBICOM
2009
ACM
13 years 11 months ago
2009
ACM
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
CGO
2008
IEEE
13 years 11 months ago
2008
IEEE
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...