86 search results - page 2 / 18 » Scaling and Packing on a Chip Multiprocessor |
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
IEEEPACT
2009
IEEE
13 years 2 months ago
2009
IEEE
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
EMSOFT
2005
Springer
13 years 10 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
GLVLSI
2010
IEEE
13 years 5 months ago
2010
IEEE
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...