35 search results - page 1 / 7 » Scan Test Planning for Power Reduction |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
ICCD
2003
IEEE
13 years 10 months ago
2003
IEEE
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...