221 search results - page 2 / 45 » Scheduling instruction effects for a statically pipelined pr... |
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
EUROPAR
2005
Springer
13 years 10 months ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
ASAP
2000
IEEE
13 years 8 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
IEEEPACT
2006
IEEE
13 years 10 months ago
2006
IEEE
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...