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» Secure Partial Reconfiguration of FPGAs
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CSREAESA
2006
13 years 7 months ago
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs
Abstract
Daniel T. Milton, Sachin Dhingra, Charles E. Strou...
IJES
2006
99views more  IJES 2006»
13 years 5 months ago
Dynamic reconfiguration for management of radiation-induced faults in FPGAs
This paper describes novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex V1000 FPGAs to manage single-event upset (SEU) faults due to rad...
Maya Gokhale, Paul Graham, Michael J. Wirthlin, Da...
DFT
2007
IEEE
152views VLSI» more  DFT 2007»
13 years 9 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...
FPL
2004
Springer
147views Hardware» more  FPL 2004»
13 years 11 months ago
Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs
Current trends show that partial and dynamic reconfiguration can be used in adaptive systems. These systems are able to adapt themselves to the demand of their environment during r...
Brandon Blodget, Christophe Bobda, Michael Hü...
ARC
2008
Springer
89views Hardware» more  ARC 2008»
13 years 7 months ago
A Networked, Lightweight and Partially Reconfigurable Platform
Abstract. In this paper we present a networked lightweight and partially reconfigurable platform assisted by a remote bitstreams server. We propose a software and hardware architec...
Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet