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DFT
2007
IEEE

TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs

13 years 7 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Soft Errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.
Cristiana Bolchini, Antonio Miele, Marco D. Santam
Added 14 Aug 2010
Updated 14 Aug 2010
Type Conference
Year 2007
Where DFT
Authors Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio
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