46 search results - page 7 / 10 » Self Testing SoC with Reduced Memory Requirements and Minimi... |
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
ASPLOS
2012
ACM
12 years 1 months ago
2012
ACM
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...
DATE
2002
IEEE
13 years 11 months ago
2002
IEEE
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
ITC
1994
IEEE
13 years 10 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
GLVLSI
2007
IEEE
14 years 15 days ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...