49 search results - page 4 / 10 » Sensitivity-Based Gate Delay Propagation in Static Timing An... |
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...