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ITC
2003
IEEE
167views Hardware» more  ITC 2003»
13 years 10 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
DATE
2006
IEEE
129views Hardware» more  DATE 2006»
13 years 11 months ago
Non-gaussian statistical interconnect timing analysis
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
13 years 11 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
DAC
2007
ACM
14 years 6 months ago
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis
It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a f...
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nass...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
13 years 11 months ago
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits
In this paper we present a method which allows the statistical analysis of nanoelectronic Boolean networks with respect to timing uncertainty and noise. All signals are considered...
Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred G...