22 search results - page 4 / 5 » Sequential circuit test generation using dynamic state trave... |
VLSID
2007
IEEE
14 years 6 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
Many DTM schemes rely heavily on the accurate knowledge of the chip's dynamic thermal state to make optimal performance/ temperature trade-off decisions. This information is ...