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» Short circuit power consumption of glitches
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DAC
1999
ACM
14 years 5 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
13 years 2 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong
ASPDAC
2007
ACM
117views Hardware» more  ASPDAC 2007»
13 years 8 months ago
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms
An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage valu...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
CHES
2005
Springer
82views Cryptology» more  CHES 2005»
13 years 10 months ago
Masking at Gate Level in the Presence of Glitches
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
Wieland Fischer, Berndt M. Gammel
ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
13 years 8 months ago
Estimation and bounding of energy consumption in burst-mode control circuits
This paper describes two techniques to quantify energy consumption of burst-modeasynchronous(clock-less)controlcircuits. The circuit specifications consideredare extended burst-m...
Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick,...