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GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
DAC
2007
ACM
14 years 5 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
SIGGRAPH
1995
ACM
13 years 8 months ago
A signal processing approach to fair surface design
In this paper we describe a new tool for interactive free-form fair surface design. By generalizing classical discrete Fourier analysis to two-dimensional discrete surface signals...
Gabriel Taubin
ASAP
1997
IEEE
156views Hardware» more  ASAP 1997»
13 years 9 months ago
Design methodology for digital signal processing
Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challeng...
Gerhard Fettweis
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 9 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen