21 search results - page 1 / 5 » Signal integrity management in an SoC physical design flow |
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC desi...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...