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FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
13 years 9 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic
PVLDB
2008
123views more  PVLDB 2008»
13 years 4 months ago
Efficient implementation of sorting on multi-core SIMD CPU architecture
Sorting a list of input numbers is one of the most fundamental problems in the field of computer science in general and high-throughput database applications in particular. Althou...
Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, ...
VLSISP
2002
93views more  VLSISP 2002»
13 years 5 months ago
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...
Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. ...
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
13 years 11 months ago
Modeling of MOS transistors based on genetic algorithm and simulated annealing
— A novel method to extract the efficient model for Metal-Oxide-Semiconductor (MOS) transistors in order to satisfy a specific accuracy is presented. The approach presented here ...
Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Ame...