11 search results - page 1 / 3 » Simultaneous Routing and Buffer Insertion with Restrictions ... |
DAC
1999
ACM
14 years 5 months ago
1999
ACM
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...