17 search results - page 3 / 4 » Simultaneous Wire Sizing and Wire Spacing in Post-Layout Per... |
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the t...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
ICCAD
1991
IEEE
13 years 8 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...