78 search results - page 15 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
BWCCA
2010
13 years 1 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
JCP
2008
13 years 6 months ago
2008
In sensor networks, continuous query is commonly used for collecting periodical data from the objects under monitoring. This sort of queries needs to be carefully designed, in orde...
JCM
2010
13 years 4 months ago
2010
— This paper presents a resource-efficient protocol for opportunistic routing in delay-tolerant networks (DTN). First, our approach exploits the context of mobile nodes (speed, ...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
NOCS
2008
IEEE
14 years 18 days ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...