78 search results - page 2 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
ISPD
1997
ACM
13 years 9 months ago
1997
ACM
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
TC
2008
13 years 5 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
JCP
2008
13 years 5 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...