51 search results - page 2 / 11 » Simultaneous driver and wire sizing for performance and powe... |
JCP
2008
13 years 5 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...