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ICCAD
1996
IEEE

An efficient approach to simultaneous transistor and interconnect sizing

10 years 7 months ago
An efficient approach to simultaneous transistor and interconnect sizing
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an ecient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buer and wire sizing problem for real designs, it reduces the maximum delay by up to 16.1%, and more signi cantly, reduces the power consump
Jason Cong, Lei He
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where ICCAD
Authors Jason Cong, Lei He
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