51 search results - page 3 / 11 » Simultaneous driver and wire sizing for performance and powe... |
TVLSI
2010
13 years 14 days ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
DAC
1999
ACM
13 years 10 months ago
1999
ACM
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...