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ISLPED
1999
ACM
177views Hardware» more  ISLPED 1999»
10 years 5 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can signi´Čücantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
Vijay Sundararajan, Keshab K. Parhi
DAC
2004
ACM
11 years 2 months ago
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant e
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
10 years 7 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi
JCSC
2002
129views more  JCSC 2002»
10 years 28 days ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
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