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ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 1 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow
DAC
1994
ACM
13 years 9 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
Sudip Nag, Rob A. Rutenbar
IPPS
1998
IEEE
13 years 9 months ago
Partial Rearrangements of Space-Shared FPGAs
Abstract Oliver Diessel1 and Hossam ElGindy2 1Department of Computer Science and Software Engineering 2Department of Electrical and Computer Engineering The University of Newcastle...
Oliver Diessel, Hossam A. ElGindy
ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
14 years 1 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
SAMOS
2007
Springer
13 years 11 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...