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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 5 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
13 years 10 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
CF
2005
ACM
13 years 7 months ago
Controlling leakage power with the replacement policy in slumberous caches
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Nasir Mohyuddin, Rashed Bhatti, Michel Dubois
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 10 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
CF
2005
ACM
13 years 7 months ago
Skewed caches from a low-power perspective
The common approach to reduce cache conflicts is to increase the associativity. From a dynamic power perspective this associativity comes at a high cost. In this paper we present...
Mathias Spjuth, Martin Karlsson, Erik Hagersten