Sciweavers

20 search results - page 1 / 4
» Soft Error Hardening for Asynchronous Circuits
Sort
View
DFT
2007
IEEE
100views VLSI» more  DFT 2007»
13 years 11 months ago
Soft Error Hardening for Asynchronous Circuits
Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao
ICCD
2008
IEEE
157views Hardware» more  ICCD 2008»
14 years 1 months ago
Power-aware soft error hardening via selective voltage scaling
—Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking...
Kai-Chiang Wu, Diana Marculescu
DSN
2008
IEEE
13 years 11 months ago
Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...
Xin Fu, Tao Li, José A. B. Fortes
JOLPE
2010
97views more  JOLPE 2010»
13 years 3 months ago
Low-Power Soft Error Hardened Latch
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
Hossein Karimiyan Alidash, Vojin G. Oklobdzija
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
13 years 11 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...