35 search results - page 1 / 7 » Soft Error-Aware Power Optimization Using Gate Sizing |
PATMOS
2007
Springer
13 years 10 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
TCAD
2008
13 years 4 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
ISPD
2012
ACM
12 years 4 days ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
TVLSI
2008
13 years 4 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...