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IJCES
2002
100views more  IJCES 2002»
13 years 5 months ago
Neural Network Decoders for Linear Block Codes
This paper presents a class of neural networks suitable for the application of decoding error-correcting codes.The neural model is basically a perceptron with a high-order polynom...
Ja-Ling Wu, Yuen-Hsien Tseng, Yuh-Ming Huang
DFT
2004
IEEE
90views VLSI» more  DFT 2004»
13 years 9 months ago
An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems
In this paper, a simple codec algorithm based on Reed-Solomon (RS) codes is proposed for erasure correcting in RAID (Redundant Array of Independent Disks) level 6 systems. Unlike ...
Ping-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen ...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
13 years 11 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
ICIP
2007
IEEE
13 years 11 months ago
Distributed Coding of Multiresolution Omnidirectional Images
This paper addresses the problem of compact representation of a 3D scene, captured by distributed omnidirectional cameras. As the images from the sensors are likely to be correlat...
Vijayaraghavan Thirumalai, Ivana Tosic, Pascal Fro...
TCAD
2011
12 years 11 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...