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ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 7 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
RTSS
2006
IEEE
13 years 11 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
NOCS
2008
IEEE
13 years 12 months ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani
EGH
2004
Springer
13 years 11 months ago
Realtime ray tracing of dynamic scenes on an FPGA chip
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
Jörg Schmittler, Sven Woop, Daniel Wagner, Wo...
CCECE
2006
IEEE
13 years 11 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya