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» Software-Based Delay Fault Testing of Processor Cores
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ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
13 years 11 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
13 years 10 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
13 years 11 months ago
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
Nektarios Kranitis, Andreas Merentitis, N. Laoutar...
SAC
2008
ACM
13 years 4 months ago
A hybrid software-based self-testing methodology for embedded processor
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
13 years 11 months ago
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, ...