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ETS
2007
IEEE
128views Hardware» more  ETS 2007»
13 years 6 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
13 years 10 months ago
Software-based self-test of processors under power constraints
Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initiali...
Jun Zhou, Hans-Joachim Wunderlich
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
13 years 10 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 6 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
13 years 11 months ago
Performance optimal speed control of multi-core processors under thermal constraints
Abstract—Advances in chip-multiprocessor processing capabilities has led to an increased power consumption and temperature hotspots. Maintaining the on-chip temperature is import...
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Ch...