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» Specification Test Compaction for Analog Circuits and MEMS
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DATE
2005
IEEE
97views Hardware» more  DATE 2005»
13 years 11 months ago
Specification Test Compaction for Analog Circuits and MEMS
Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Lar...
ET
2002
64views more  ET 2002»
13 years 5 months ago
Structural Fault Based Specification Reduction for Testing Analog Circuits
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
CASES
2006
ACM
13 years 11 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 9 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
DATE
2002
IEEE
97views Hardware» more  DATE 2002»
13 years 10 months ago
Analog IP Testing: Diagnosis and Optimization
In this paper, we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in th...
Carlo Guardiani, Patrick McNamara, Lidia Daldoss, ...