Sciweavers

10 search results - page 2 / 2
» Speeding Up Bipartite Modular Multiplication
Sort
View
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
13 years 11 months ago
A fast dual-field modular arithmetic logic unit and its hardware implementation
— We propose a fast Modular Arithmetic Logic Unit (MALU) that is scalable in the digit size (d) and the field size (k). The datapath of MALU has chains of Carry Save Adders (CSA...
Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
ESAS
2007
Springer
13 years 11 months ago
Enabling Full-Size Public-Key Algorithms on 8-Bit Sensor Nodes
Abstract. In this article we present the fastest known implementation of a modular multiplication for a 160-bit standard compliant elliptic curve (secp160r1) for 8-bit micro contro...
Leif Uhsadel, Axel Poschmann, Christof Paar
AMC
2005
256views more  AMC 2005»
13 years 5 months ago
Improved DSA variant for batch verification
Batch verification is a method to verify multiple signatures at once. There are two issues associated with batch verification. One is the security problem and the other is the com...
Chu-Hsing Lin, Ruei-Hau Hsu, Lein Harn
ICRA
2006
IEEE
127views Robotics» more  ICRA 2006»
13 years 11 months ago
Multimode Locomotion via SuperBot Robots
– This paper presents a modular and reconfigurable robot for multiple locomotion modes based on reconfigurable modules. Each mode consists of characteristics for the environment ...
Wei-Min Shen, Maks Krivokon, Harris Chiu, Jacob Ev...
AROBOTS
2006
94views more  AROBOTS 2006»
13 years 5 months ago
Multimode locomotion via SuperBot reconfigurable robots
Abstract One of the most challenging issues for a selfsustaining robotic system is how to use its limited resources to accomplish a large variety of tasks. The scope of such tasks ...
Wei-Min Shen, Maks Krivokon, Harris Chiu, Jacob Ev...